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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity jiaotongdeng is
Port ( rst : in std_logic;
clk : in std_logic;
fmq : out std_logic;
led : out std_logic_vector(5 downto 0);
Ledb : out std_logic_vector(1 downto 0);
LedOut : out std_logic_vector(7 downto 0));
end jiaotongdeng;
architecture Behavioral of jiaotongdeng is
signal count1: std_logic_vector(25 downto 0);
signal count2: std_logic_vector(7 downto 0);
signal countdelay: std_logic_vector(25 downto 0);
signal count: std_logic_vector(1 downto 0);
signal datain: std_logic_vector(3 downto 0);
signal data1 : std_logic_vector(3 downto 0);
signal data2 : std_logic_vector(3 downto 0);
type st is(westg,westy,southg,southy);
signal my_st:st;
begin
process(clk,rst)
begin
if rst='0' then
count1'0');
count
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